Welcome to Adwait's Homepage
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Adwait Jog, Ph.D. (Penn State)Assistant ProfessorDepartment of Computer ScienceCollege of William & MaryMcGlothlin-Street Hall 111Williamsburg, VA 23187
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ajog@wm.edu, About
I am an assistant professor in the Department of Computer Science
at College of William & Mary (W&M) in Virginia, USA. At W&M, I
am leading the Insight Computer Architecture Lab with
the goal to generate insights, which would help in architecting future computers that are
more energy-efficient, capable, reliable, and secure.
I am always looking for self-motivated and talented students to join my lab. We have several funded RA positions. Send me a brief email to start the conversation. All graduate admissions are formally managed by W&M CS department.
Recent News
I delivered talks at the ECE departments of NCSU and GWU on memory bandwidth management techniques for performance and security. Talk slides are available here.
I delivered talks at Intel and Cisco on our recent work on GPU security.
W&M published a featured news item on my group's work and recently granted NSF CAREER Award.
I will be teaching a short GPU course at the computer architecture summer school organized annually by HiPEAC. See more details here. Registration details can be found here. Stay tuned for course materials.
I am grateful and honored to receive NSF CAREER Award 2018. Over the next five years, this award will support my group to research on large-scale GPU-based systems and to pursue my teaching/outreach goals. Thanks NSF!
Co-organized second version of the workshop on minimizing data movement (Min-Move). It was co-located with ASPLOS 2018.The workshop was a great success.
As a part of outreach, I gave a talk titled Computer Science: Myths, Challenges, and Opportunties to high school students attending Focusing on the Future (FOF) conference organized by School of Education, W&M.
Paper accepted in ASPLOS 2018.
Our newly formed Insight Computer Architecture Lab will showcase two accepted papers at HPCA 2018.
We have developed new memory bandwidth management techniques for efficient and fair multi-application execution in GPUs.
We have developed new randomized coalescing mechanisms for efficiently balancing performance and security in GPUs.
Invited to be on the Program Committees of ISPASS 2018 and GPGPU-11 2018. Submit your best work!
Co-organized a workshop on minimizing data movement (Min-Move 2017) co-located with PACT 2017. The workshop was a great success.
As a part of outreach, I gave a talk on Career Opportunities in CS to middle school students attending Focusing on the Future (FOF) conference organized by School of Education, W&M.
Received NSF SHF Award 2017, PI. Thanks NSF!
Received NSF CRII Award 2017, PI. Thanks NSF!
Papers accepted in HPCA 2017, VLSID 2017, and ISVLSI 2017
Papers accepted in IISWC 2016, 2x PACT 2016, MICRO 2016, and SIGMETRICS 2016.
Served on the Program Committees of HPCA 2018, MICRO 2017 (ERC), DSN 2017, HPDC 2017, GPGPU 2017, and NAS 2017.
Selected Publications (complete list)
(HPCA 2018) Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management
(HPCA 2018) RCoal: Mitigating GPU Timing Attack via Subwarp-based Randomized Coalescing Techniques
(ASPLOS 2018) MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency
(HPCA 2017) Controlled Kernel Launch for Dynamic Parallelism in GPUs
(MICRO 2016) Zorua: A Holistic Approach to Resource Virtualization in GPUs
(PACT 2016) Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities
(PACT 2016) μC-States: Fine-grained GPU Datapath Power Management
(SIGMETRICS 2016) Exploiting Core Criticality for Enhanced GPU Performance
(MICRO 2014) Managing GPU Concurrency in Heterogeneous Architectures
(PACT 2014) Trading Cache Hit Rate for Memory Performance
(PACT 2013) Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs
(ISCA 2013) Orchestrated Scheduling and Prefetching for GPGPUs
(ASPLOS 2013) OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU performance
(DAC 2012) Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs