CSCI 424 : Computer Architecture, Fall 2017

General Information

Prerequisites and Course Description

Prerequisite(s): CSCI 304 and either CSCI 301 or CSCI 303

This course will introduce principles of computer design. The students will apply their knowledge of digital logic design to understand the high-level interactions between different computer system hardware components. Specifically, this course will cover various computer architecture aspects related to MIPS ISA, single-cycle data-path design, multiple-cycle design, pipelining, memory hierarchy, and multiprocessor architecture.

Textbook and Resources

Grade Distribution

Collaboration and Classroom Policies

Submissions, Grading, and Deadlines


Tentative Schedule (Will keep changing regularly)

Week Date Agenda Readings HW Quiz Notes
Week 1   Aug 31   Administrativia and Introductions       Quiz 1 Out   First Day of class.  
Week 2   Sep 5   Introduction, Abstractions, and Technology   Chapter 1       Download/Install MARS and run sample codes to prepare for upcoming homeworks.  
Sep 7   Introduction, Abstractions, and Technology     HW 1 Out   Quiz 1 Due   Sep 8 is the add/drop deadline.  
Week 3   Sep 12   MIPS ISA   Appendix A        
Sep 14   MIPS ISA     HW 1 Due/HW2 Out   Quiz 2 Out    
Week 4   Sep 19   MIPS ISA   Chapter 2        
Sep 21   MIPS ISA       Quiz 2 Due    
Week 5   Sep 26   MIPS Datapath Components   Appendix B.1 -- B.3 and B.7--B.9   HW 2 Due / HW3 Out   Quiz 3 Out    
Sep 28   Single Cycle Datapath Design   Chapter 4.1 -- 4.3        
Week 6   Oct 3   Intro to Pipelining          
Oct 5   Pipelining and Hazards   Chapter 4.4 -- 4.7   HW3 Due / HW4 Out   Quiz 3 Due / Quiz 4 Out    
Week 7   Oct 10   Pipelining and Hazards         Practice exam and solutions are out.
Oct 12   Mid-term Review     HW 4 Due   Quiz 4 Due    
Week 8   Oct 17   No class (Fall Break)          
Oct 19   In-class Mid-term Examination.         Mid-term exam will include all the material covered until the Fall break. Exam duration is 75 minutes. One A4-sized cheat sheet is allowed. Yes, you can use both sides of the page.  
Week 9   Oct 24   No Class         Instructor on Travel  
Oct 26   Pipelining and Related Issues   Chapter 4.8   HW#5 is out     In-class Analysis of Mid-term. Oct 27 is the withdraw deadline.  
Week 10   Oct 31   Memory Hierarchy (Caches)   Chapter 5.1 -- 5.4        
Nov 2   Memory Hierarchy (Caches)     HW#5 is due      
Week 11   Nov 7   Memory Hierarchy (Caches)     HW#6 is out  Quiz 5 is out   
Nov 9   Memory Hierarchy (DRAM)          
Week 12   Nov 14   Virtual Memory and TLBs   Chapter 5.6 -- 5.8     Quiz 5 is due / Quiz 6 is out    
Nov 16   Virtual Memory and TLBs     HW#6 is due / HW#7 is out      
Week 13   Nov 21   Review Session       Quiz 6 is due   Quiz review by Gurunath  
Nov 23   No class (Thanksgiving Break)          
Week 14   Nov 28   Disks and I/O   Chapter 5.11     Quiz 7 is out    
Nov 30   Multi-processors   Chapter 6.1 -- 6.5 HW#7 is due / HW#8 is out      
Week 15   Dec 5   Multi-processors   Appendix C-2        
Dec 7   Final-exam review and wrap-up     HW#8 is due on Dec 8th.   Quiz 7 is due.   Course evaluations are due on Dec 8
Finals   Dec 18   Comprehensive Final Exam, 2:00 to 5:00 PM, Morton 201         To be held in the Regular Classroom. (Exam Schedule). Final exam will include all material covered during the semester.  

Academic Integrity and Accommodations


The lecture slides of this course are developed based on the original lecture slides from Mary. J. Irwin (Penn State), which were adapted from Computer Organization and Design, 5th Edition, Patterson & Hennessy (P&H), Morgan Kaufmann. The course staff also acknowledges the contributions of Mary. J. Irwin, Chita Das, Yuan Xie, N. Vijaykrishnan, and other instructors and TAs at Penn State, towards developing the course material over a period of time. Some of the collaboration rules are inspired by CSE 465 course at Penn State.