CSCI 424 / CSCI 524: Computer Architecture, Fall 2016

General Information

Prerequisites and Course Description

Prerequisite(s): CSCI 304 and either CSCI 301 or CSCI 303

This course will introduce principles of computer design. The students will apply their knowledge of digital logic design to understand the high-level interactions between different computer system hardware components. Specifically, this course will cover various computer architecture aspects related to MIPS ISA, single-cycle data-path design, multiple-cycle design, pipelining, memory hierarchy, and multiprocessor architecture.

Textbook and Resources

Grade Distribution

Course Policies


Fall 2016 Schedule

Week Date Agenda Readings HW/Quiz Notes
Week 1   Aug 25   Administrativia and Introductions     Quiz 1 is out.   First Day of class.  
Week 2   Aug 30   Introduction, Abstractions, and Technology   Chapter 1     Download/install MARS and run sample codes to prepare for upcoming homeworks.  
Sep 1   Introduction, Abstractions, and Technology     HW 1 is out. Quiz 1 is due.   Sep 2 is the add/drop deadline.  
Week 3   Sep 6   MIPS ISA   Appendix A      
Sep 8   MIPS ISA     HW 1 is due. Quiz 2 is out. HW 2 is out.    
Week 4   Sep 13   MIPS ISA   Chapter 2   Quiz 2 is due.    
Sep 15   MIPS ISA        
Week 5   Sep 20   MIPS Datapath Components   Appendix B.1 -- B.3 and B.7--B.9   HW 2 is due. Quiz 3 and HW 3 are out.    
Sep 22   Single Cycle Datapath Design   Chapter 4.1 -- 4.3      
Week 6   Sep 27   MIPS Review     Quiz 3 is due. HW 3 is due.   Instructor is out of town. Mohamed (TA) will take the class. HW 3 deadline is extended till Friday, Sept 30th  
Sep 29   Single Cycle Datapath Design     Quiz 4 is out. HW 4 is out.    
Week 7   Oct 04   Intro to Pipelining   Chapter 4.4 -- 4.7   Practice exam and solutions are out.
Oct 06   Mid-term Review     Quiz 4 is due. HW 4 is due.    
Week 8   Oct 11   No class (Fall Break)        
Oct 13   In-class Mid-term Examination.       Mid-term exam will include all the material covered until the Fall break. Exam duration is 75 minutes.  
Week 9   Oct 18   Pipelining and Related Issues   Chapter 4.8     Mid-term Analysis will be discussed in the class.  
Oct 20   Pipelining and Related Issues     Quiz 5 and HW5 are out. Oct 21 is the withdraw deadline.  
Week 10   Oct 25   Memory Hierarchy (Caches)   Chapter 5.1 -- 5.4      
Oct 27   Memory Hierarchy (Caches)     Quiz 5 is due.    
Week 11   Nov 1   Memory Hierarchy (DRAM)     HW5 is due.  
Nov 3   Memory Hierarchy (DRAM)     Quiz 6 and HW6 are out.  
Week 12   Nov 8   Virtual Memory and TLBs        
Nov 10   Virtual Memory and TLBs   Chapter 5.6 -- 5.8   Quiz 6 and HW6 are due. We discussed new problems on Virtual Memory and Caching
Week 13   Nov 15   Disks and I/O   Chapter 5.11      
Nov 17   ----       Class and office hours are cancelled;
Week 14   Nov 22   Multi-processors   Chapter 6.1 -- 6.5 Quiz 7 and HW 7 are due.  
Nov 24   No class (Thanksgiving Break)        
Week 15   Nov 29   Multi-processors   Appendix C-2      
Dec 1   Final-exam review and wrap-up     HW 8 is due on Dec 2 Course evaluations are due on Dec 2
Finals   Dec 14   Comprehensive Final Exam, 2:00 to 5:00 PM, ISC 2280       To be held in the Regular Classroom. (Fall 2016 Exam Schedule). Final exam will include all material covered during the semester.  

Academic Integrity and Accommodations


The lecture slides of this course are developed based on the original lecture slides from Mary. J. Irwin (Penn State), which were adapted from Computer Organization and Design, 5th Edition, Patterson & Hennessy (P&H), Morgan Kaufmann. The course staff also acknowledges the contributions of Mary. J. Irwin, Chita Das, Yuan Xie, N. Vijaykrishnan, and other instructors and TAs at Penn State, towards developing the course material over a period of time.