Time and Location: Tuesday/Thursday 3:30PM-4:50PM, Washington Hall 310
Instructor: Adwait Jog (Personal Website)
Office hours: Tues/Thu 10:30AM-noon or by appointment, McGl 111
Email: adwait@cs.wm.edu
Deadlines: Jan 29 (add/drop deadline) and Mar 18 (withdraw deadline)
Students are expected to have a good understanding of the basic computer organization and design. Please talk to the instructor if you do not satisfy this requirement.
This course provides an in-depth understanding of the architectural and micro-architectural details of a general purpose graphics processing unit (GPU). It also provides an in-depth coverage of important research issues associated with GPU computing by covering a range of latest papers that have appeared in leading international journals and conferences. Students are expected to read a variety of papers, critique them, and present them in the front of the class. In addition, students are expected to complete a semester-long research project and simulation-based assignments.
(I) Paper critiques: 10%
(II) In-Class Presentations: 20%
(III) Simulation-based Assignments: 30%
(IV) Semester-long Research Project: 40%
In-Class Presentations will be uploaded in a shared Box folder visible to all students.
Critique and Report Submissions via Box. A separate Box folder will be shared with the instructor and the student.
Final grade submission via Banner.
All students are required to submit a detailed critique for each paper we discuss in the class. However, the student who presents the paper in-class is not allowed to submit the critique for that particular paper. Deadline for critique submission is one week from when the paper is discussed completely in the class. Please submit any FIVE critiques in the PDF format.
Submission Format: Each critique should not exceed one-page and must consists of four sections: 1) paper summary (2-3 lines), 2) strengths (2-3 lines), 3) weaknesses (2-3 lines), and 4) detailed comments (rest of the page). More details are already discussed in class and associated slides are submitted to the box folder (shared with students).
No collaboration is allowed on critiques.
Each student will present a maximum of two papers throughout the semester. If you plan to audit the course, you are required to present at least two papers. When you present a paper, be prepared to answer a variety of questions asked by the instructor or other fellow students. The goal is to make class lively. A list of papers will be provided to students. They can choose from that list or come up with their own suggestions. Suggestions would need approval from the instructor.
In-Class Paper Presentations: I expect students to first present necessary
background (~15 minutes) and then paper details (~25 minutes). The remaining
time will be for discussion driven by the fellow students and the instructor.
Assignments will be given based on the GPGPU-Sim simulator. GPGPU-Sim Installation guide (for bg machines at CS, WM) is here. No collaboration is allowed on assignments.
Students are expected to perform a semester-long research
project. All projects need to be approved by the instructor.
Please contact the instructor early to brainstorm potential
project ideas.
Project Timeline
Phase 1 – Project Determination: (Deadline: Feb 6); Please send an email to the instructor by
the deadline containing: 1) Project Name (think of this as your paper/report title), 2) Problem Statement,
3) Expected Infrastructure Platform Required, 4) Possible Outcomes and Deliverables.
Phase 2 – Determination of (more) concrete project goals and Infrastructure Setup (Deadline: Feb 25 ); Please meet the instructor during office hours to discuss the status of your project.
Phase 3 – Motivation Results (Deadline: April 5); Please meet the instructor during office hours to discuss the status of your project.
Phase 4 – Final Project Report (Deadline: May 10); Please email your final project report in PDF format. Please use the standard LaTeX or Word ACM templates. The PDF should have these sections: 1) Problem Statement, 2) Introduction, 3) Background and Related Work, 4) Motivation Results, 5) Implementation Details, 6) Infrastructure Details, 7) Final Results, and 8) Conclusions.
GPU Core Design
GPU Warp Scheduler Design
GPU Thread block Scheduler Design
GPU Cache Design
GPU Memory System Design (incl. emerging memory technology design)
GPU Processing-in-Memory
GPU Interconnect Design
GPU Reliability
Multi-GPU systems
Multi-context GPU Architecture
Mobile GPU Architecture
Approximate GPU Architecture
Heterogeneous GPU platforms that incorporate GPUs
GPGPU-Sim, A GPU Simulator (models NVIDIA-style GPUs). Also, look at GPU-Wattch, A GPU Power Model
MacSim, A trace-driven CPU/GPU simulator
SASSI, A Flexible GPGPU Instrumentation Tool
MAFIA, A Multiple Application/Context Framework for GPU architectures
Multi2sim, A CPU/GPU Simulator (models AMD-style GPUs)
CPU-GPU Simulator, A Trace/Execution Driven CPU-GPU Heterogeneous Architecture Simulator
GemDroid, A Mobile Architecture Simulator (GEM5 + Android Emulator)
Date | Agenda | Notes |
---|---|---|
Jan 21 | Administrativia and Introductions | HW#0 Out |
Jan 26 | Introduction to CUDA (1) | HW#1 Out |
Jan 28 | Introduction to CUDA (2) | HW#0 Due |
Feb 2 | Overview of GPU Architecture | HW#1 Due |
Feb 4 | Overview of GPGPU-Sim | HW#2 Out |
Feb 9 | GPU Micro-architecture/Architecture (1) | |
Feb 11 | GPU Micro-architecture/Architecture (2) | |
Feb 16 | GPU Memory System (1) | HW#2 Due |
Feb 18 | GPU Memory System (2) | |
Feb 23 | Advanced GPU Topics (1) | HW#3 Out |
Feb 25 | Advanced GPU Topics (2) | |
Mar 1 | Presenter: Bin Nie, GPU Reliability | |
Mar 3 | Presenter: Lingfei Wu | |
Mar 8 | Spring break, no classes | |
Mar 10 | Spring break, no classes | |
Mar 15 | Presenter: James Bieron, Paper: [P1] | In-class Presentations Start, HW#3 Due |
Mar 17 | Presenter: Haonan Wang, Paper: [P2] | |
Mar 22 | Presenter: Fan Luo, Paper: [P3] | Critique [P1] Due, HW#4 Out |
Mar 24 | Presenter: Haonan Wang, Paper: [P4] | Critique [P2] Due |
Mar 29 | Presenter: Fan Luo, Paper: [P5] | Critique [P3] Due |
Mar 31 | Presenter: Shan Wang, Paper: [P6] | Critique [P4] Due |
Apr 5 | Presenter: Yiqiang Lin, Paper: [P7] | Critique [P5] Due, HW#4 Due |
Apr 7 | Presenter: Mohamed Assem Ibrahim, Paper: [P8] | Critique [P6] Due |
Apr 12 | Presenter: James Bieron, Paper: [P9] | Critique [P7] Due |
Apr 14 | Presenter: Mohamed Assem Ibrahim, Paper: [P10] | Critique [P8] Due |
Apr 19 | Presenter: Yiqiang Lin, Paper: [P11] | Critique [P9] Due |
Apr 21 | Presenter: Shan Wang, Paper: [P12] | Critique [P10] Due |
Apr 26 | Final Project Presentations | Critique [P11] Due |
Apr 28 | Final Project Presentations | Critique [P12] Due |
P1: Architectural Support for Address Translation on GPUs, ASPLOS 2014
P2: Improving GPU Performance via Large Warps and Two-Level Warp Scheduling, MICRO 2011
P3: Cache-Conscious Wavefront Scheduling, MICRO 2012
P4: WarpPool: sharing requests with inter-warp coalescing for throughput processors, MICRO 2015
P5: Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow, MICRO 2007
P6: GPU Register File Virtualization, MICRO 2015
P7: Throughput-Effective On-Chip Networks for Manycore Accelerators, MICRO 2010
P8: Cache Coherence for GPU Architectures, HPCA 2013
P9: Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution, MICRO 2014
P10: A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps, ISCA 2015
P11: Neural acceleration for GPU throughput processors, MICRO 2015
P12: A Complete Key Recovery Timing Attack on a GPU, HPCA 2016
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